1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method of testing the same, in particular a semiconductor integrated circuit device having a first chip that is externally accessible and a second chip that cannot be accessed directly from the outside, and a method of testing the same.
2. Description of Related Art
A semiconductor integrated circuit device capable of achieving a large-scale system in a single package by adopting a SiP (System in Package) architecture in which plural chips having different functions such as a memory chip and a logic chip are mixed and mounted in the single package has been proposed. It has been desired to reduce package size and the number of input/output terminals in such semiconductor integrated circuit devices having the SiP architecture. To answer such requirements, a structure has been adopted in which no external terminals are provided for a chip that need not be externally accessed as the semiconductor integrated circuit device functions as a finished product.
However, when a semiconductor integrated circuit device contains a chip in such a manner where no external terminal is provided for the chip, it becomes very difficult to carry out a test on that chip after the package is assembled. Accordingly, a through circuit or the like is provided in another chip that can be directly accessed from the outside as an access path to the chip for which no external terminal is provided.
FIG. 7 shows a structural block diagram of a semiconductor integrated circuit device 1 and its connection relationship with a tester 20 that carries out a test on a memory chip contained in the semiconductor integrated circuit device 1 in the related art. As shown in FIG. 7, the semiconductor integrated circuit device 1 in the related art includes a logic chip 30 and a SDR (Single Data Rate) memory chip 40, both of which are mounted in a single package 10. Note that the logic chip 30 corresponds to the chip that can be directly accessed from the outside, and the memory chip 40 corresponds to the chip that cannot be directly accessed from the outside.
In general, it is very difficult to test a memory chip through the logic terminals in a SIP in which the external terminals do not include any terminal dedicated to the memory chip as in the case of the above-described package 10. Therefore, a through circuit 50 for a test is provided in the logic chip 30 so that a memory test can be carried out by accessing to the SDR memory chip 40 through that through circuit.
The through circuit 50 includes flip-flops conFF1 and conFF2 for address and control signals (“add/conr1” in FIG. 7) flip-flops WrFF1 and WrFF2 for write data, flip-flops ReFF1 and ReFF2 for read data, and various buffers. As can be seen from FIG. 7, the SDR memory chip 40 is not directly connected to any external terminals of the package 10, and access to the SDR memory chip 40 are entirely carried out through the through circuit 50.
A terminal 21 for address/control signals of a tester 20, a terminal 22 for data, a control clock terminal 23, a bus control signal terminals 24 and 25 for write data are connected to terminals 11-15 of the package 10. Furthermore, the terminals 11-15 are connected to terminals 31-35 of the logic chip 30. Signals output from the tester 20 pass through the through circuit 50 and are output from terminals 36-38 of the logic chip 30, and then input to a terminal 41 for address and control signals, a terminal 42 for data, and a control clock terminal 43 of the SDR memory chip 40. Meanwhile, output data signals from the data terminal 42 of the SDR memory chip 40 are input to the terminal 37 of the logic chip 30, and pass through the terminal 32 of the logic chip 30 and the terminal 12 of the package 10 and are input to the terminal 22 of the package 10.
When an operational test is carried out on the SDR memory chip 40 at high speed, the test is carried out in such a manner that all data signals and control signals are synchronized to a control clock CK through flip-flops (FFs) in the logic chip 30 as shown in FIG. 7. In the structure of this related-art example, one write data is input from the through circuit 50 to the SDR memory chip 40 for each clock of the control clock CK. Furthermore, one read data is output from the SDR memory chip 40 for each clock of the control clock CK.
Incidentally, DDR (Double Data Rate) memories, whose transfer rates are about twice as fast as those of SDR memories, have been increasingly used as memories in recent years. A DDR memory has an additional input/output terminal for a signal called “data strobe” in comparison with a SDR memory, and carries out data input/output in synchronization with the rising edge or the falling edge of this data strove signal. The input/output terminal for this data strove (DQS) signal is called a “DQS pin”. The DQS signal, which is input from the DQS pin, is necessary to secure a set-up margin (tDS) and a hold margin (tDH) with respect to input data in write operation of a DDR memory.
Note that Japanese Unexamined Patent Application Publication No. 2004-158098 (Patent document 1) discloses a technique for a SiP-type semiconductor device using an SDR memory. Furthermore, U.S. Patent Application Publication No. 2005/0289428A1 (Patent document 2) discloses a technique for a SiP-type semiconductor device using a DDR memory.